FIG. 1 shows an integrated semiconductor memory device 100 designed, for example as a DRAM (dynamic random access memory) semiconductor memory. The integrated semiconductor memory device includes a memory cell array 10, in which DRAM memory cells SZ are arranged in matrix-type fashion along word lines WL and bit lines BL. A DRAM memory cell includes a selection transistor AT and a storage capacitor SC. In the event of a read or write access to the memory cell SZ, a corresponding control potential that switches the selection transistor AT into the on state is fed in onto the word line connected to the memory cell. As a result, the storage capacitor is connected to the bit line BL in low-resistance fashion via the turned-on path of the selection transistor.
In a write access operation, a datum D present at a data terminal DQ is stored in the memory cell SZ by a high or low voltage potential being fed in onto the bit line BL connected to the memory cell from a sense amplifier (not illustrated in FIG. 1). Consequently, a high or low charge level is stored on the storage capacitor SC in a manner dependent on the datum present at the data terminal DQ.
In the event of a read access, the storage capacitor is discharged via the turned-on selection transistor, so that a potential increase or potential decrease arises on the bit line BL. The potential shift on the bit line is assessed by the sense amplifier connected to the bit line and the datum D is correspondingly output with a high or low voltage level to the data terminal DQ.
For the selection of a memory cell within a memory cell array constructed in rows and columns, an address ADS is applied to an address terminal A30. The address is buffer-stored in an address register 30, which includes an address part X for selecting a word line of the memory cell array and an address part Y for selecting a bit line of the memory cell array. The memory cell connected to the crossover point of the addressed word line and the addressed bit line can thereby be selected for the read or write access.
A control unit 20 serves for controlling read and write accesses. The control unit 20 includes a supply terminal V1 for application of a supply voltage VDD and a reference terminal V2 for application of a reference voltage VSS. For controlling the read and write accesses, it has an input terminal E25 for application of a chip select signal bCS, a control terminal S20a for application of a row select signal bRAS, a control terminal S20b for application of a column select signal bCAS and a control terminal S20c for application of a write signal bWE. Read and write accesses to memory cells of the memory cell array are effected synchronously with the profile of a clock signal.
FIG. 2 shows a write and read access to a selected memory cell, the write and read access proceeding synchronously with the profile of external clock signals CLK2 and bCLK2. In order to activate a write access, an activation signal ACT is applied to the integrated semiconductor memory device in the clock period 1. The activation signal being formed from a state change of the chip select signal bCS and of the row select signal bRAS. As a result of the activation signal ACT, a word line WL of the memory cell array 10 that is selected via an address component X is driven by the control unit 20 with a control voltage in such a way that the selection transistors of the memory cells which are arranged along the selected word line are turned on. In the subsequent clock period 2, the write command WRITE is applied to the integrated semiconductor memory device, the write command including a state change of the chip select signal bCS, of the column select signal bCAS and of the write signal bWE. As a result, a bit line is selected from the selected memory cells along the selected word line, the bit line being connected to a sense amplifier (not illustrated in FIG. 1).
Via the data terminal DQ which is likewise connected to the sense amplifier, the datum D can thus be written with a high or low voltage level to the selected memory cell. FIG. 2 shows the application of a data signal to the data terminal DQ in the clock period 3.
After the write access, a precharge command PRE is applied to the control unit 20 in the clock period 6. The precharge command PRE includes a state change of the chip select signal bCS, of the row select signal bRAS and of the write signal bWE. The precharge command brings about a precharging of all the bit lines of the memory cell array to a common equalized voltage, so that a uniform potential state prevails on all the bit lines of the memory cell array. A subsequent read and write access thus cannot be corrupted by a residual voltage that is possibly present on the bit lines.
For the read access to the memory cell SZ, the activation signal ACT is once again applied to the integrated semiconductor memory device, the activation signal turning on the selection transistors of the memory cells which are arranged along the selected word line. In order to select one of the memory cells along the selected word line, the read command READ is applied to the integrated semiconductor memory device in the clock period 8. The read command READ is formed from a state change of the chip select signal bCS and of the column select signal bCAS. The bit line connected to the selected memory cell is thereupon connected to the connected sense amplifier. The sense amplifier amplifies a potential change established on the bit line connected to the selected memory cell as a result of the discharging of the storage capacitor SC, and generates the datum D with a high or low logic level at the data output DQ according to the charge state of the storage capacitor.
The circuit components of the integrated semiconductor memory device that are provided for the read and write accesses, such as row and column decoders, for example, are generally not driven directly by the external clock signal. Instead, the control unit 20 generates an internal clock signal Cint2 at an internal terminal A20a from the clock signal component CLK2 applied to an input terminal E22a and the complementary clock signal component bCLK2 applied to an input terminal E22b. In the case of an integrated semiconductor memory device with clock-synchronous access control, all the circuit components of the integrated semiconductor memory device are then operated synchronously with the profile of the internal clock signal Cint2.
The generation of the internal clock signal Cint2 is explained below with reference to FIG. 3. Within an input amplifier of the control unit 20, a level of the external clock signal CLK2 is compared with a level of the clock signal bCLK2 complementary thereto. The input amplifier is formed as a differential amplifier and generates at points of intersection between the clock signal CLK2 and the complementary clock signal bCLK2, alternately a falling or rising signal edge of the internal clock signal Cint2. FIG. 3 shows the profile of the internal clock signal Cint2 in the ideal case where the control unit 20 is driven with noise-free external clock signals CLK2 and bCLK2.
In comparison with FIG. 3, FIG. 4 shows the real signal profile of an external clock signal CLK 1 provided, for example, by a tester during a functional test of the integrated semiconductor memory device. In contrast to the ideal clock signal CLK2, an interference amplitude is superposed on the real clock signal CLK1, so that fluctuating voltage levels of the real clock signal occur. During a functional test of the integrated semiconductor memory device, the clock signal CLK1 is applied to the input terminal E22a and a clock signal bCLK 1 with a constant level is applied to the input terminal E22b. Since the input amplifier connected to the input terminals E22a and E22b is generally formed as a fast input amplifier having a high limiting frequency, voltage peaks lying above or below the constant level of the clock signal bCLK1 arise particularly during the transition of the clock signal CLK1 from a low to a high level or from a high level to a low level. As a consequence of this, the input amplifier, which is designed for high-frequency level fluctuations of the input signals, as shown in FIG. 4, generates high-frequency level fluctuations of the internal clock signal Cint1. Due to the fast input amplifiers, it can thus happen, particularly when the integrated semiconductor memory device is driven with the clock signals of a tester on which interference signals are superimposed, that an interference signal on a clock line is assessed as a clock pulse and the chip can therefore no longer operate correctly. The risk increases all the more, the higher the limiting frequency of the input amplifier is or the faster and more sensitively the input amplifier reacts to the level fluctuations of its input signal.
One of the functional tests of an integrated semiconductor memory device is the so-called bum-in test, during which the chip is operated at elevated temperature for several hours. In this case, the chip has already been fully incorporated in a housing. The burn-in test is intended to sort out early failures in the life cycle of integrated semiconductor memories. Since the test runs for a long time, many chips are operated in parallel with testers that are as cost-effective as possible. In contrast to a normal operating mode of the integrated semiconductor memory device, in which a graphics DRAM on a motherboard of a computer is driven, for example, with operating frequencies of 800 MHz, the testers used have only an operating frequency of 5 to 10 MHz and slow signal edges of up to 50 ns. Furthermore, the dense placement of the semiconductor memories on a test board during the functional test often gives rise to increased reverse voltages of up to 100 mvolts on the signal lines.